1. Field of the Invention
The present invention relates to apparatus and method for converting differential input voltage to fully balanced output currents.
More particularly, the present invention relates to an apparatus and method for converting differential input voltage to fully balanced output currents by adding/duplicating an output section of an operational transconductance amplifier.
2. Discussion of the Background
Furthermore, the present invention relates to an apparatus and method for controlling common mode component of two output currents by using a simplified common mode controlling circuit.
As an input differential voltage/output currents converter, an operational transconductance amplifier (hereinafter referred to as an "OTA") has been developed for converting input differential voltage V.sub.1 -V.sub.2 into two output currents I.sub.O1, I.sub.O2, which are assumed to be balanced around a fixed constant value of a reference current I.sub.REFCM. In the simplest version of the OTA that can convert the input differential voltage into two fully balanced output currents I.sub.o1, I.sub.o2 (hereinafter referred as a "FB-OTA") the value of a reference current I.sub.REFCM is assumed to be zero. Usually, such a FB-OTA includes load circuits which are coupled to the output terminals of the OTA, respectively. In general, each of load circuits has the same impedance.
Typically, when differential input voltage V.sub.1 -V.sub.2 is applied to the OTA, the converted output currents I.sub.O1, I.sub.O2 inevitably include common mode component due to influences of outside noises during conversion in the OTA. In particular, when the OTA, which is a part of analog system, is integrated with digital systems together on the same substrate, the converted output currents include common mode component due to noises which are generated from the digital circuits. Consequently, it has been need to take some measurements for eliminating such undesired common mode components at the output currents to make the available amplitude of a differential output voltage as large as possible.
Conventionally, a common mode control circuit has been proposed to apply to the OTA for generating a common mode feedback control signal or a common mode feedforward control signal to the OTA. The former type OTA is called as a common mode feedback controlled type OTA (hereinafter referred to as a "CMFB"-OTA). The latter type OTA is called as a common mode feedforward controlled type OTA (hereinafter referred to as a "CMFF"-OTA)
FIGS. 14-18 are related to a conventional common mode feedback controlled type fully balanced OTA implementations. FIG. 19 shows an example of a common mode feedforward controlled type fully balanced OTA implementation.
In FIG. 14, the CMFB-OTA includes an OTA (1) for converting differential input voltage V.sub.1 -V.sub.2 to two output currents I.sub.O1, I.sub.O2. and a CMFB circuit (2a) for generating common mode feedback control voltage V.sub.B to the OTA (1). The output terminals of the OTA(1) are coupled to load circuits (3a), (3b), respectively.
When the OTA(1) converts the differential input voltage V.sub.1 V.sub.2 into two output currents I.sub.O1, I.sub.O2, available from the output terminals of the OTA(1), the output voltages V.sub.O1, V.sub.O2 are produced in accordance with a respective impedance of the load circuits (3a), (3b). The CMFB circuit (2a) generates a feedback control voltage V.sub.B, which is a function of output voltages V.sub.O1, V.sub.O2, for strong suppression/elimination of a common mode component in the output currents I.sub.o1, I.sub.o2.
FIG. 15 shows a conventional circuit of the OTA (1). The OTA (1) is comprised of four PMOS transistors (Q101)-(Q104), two NMOS transistors (Q105), (Q106), four constant-current sources (101)-(104) and a resistor (R1). The input voltages V.sub.1, V.sub.2 are respectively applied to each of the gate terminals of the NMOS transistors (Q105) and (Q106). The CMFB circuit (2a) supplies a control voltage V.sub.B to a commonly coupled gate terminals of the two PMOS transistors (Q101) and (Q102) in the OTA(1). A predetermined voltage V.sub.BO is applied to the respective gate terminals of the another two PMOS transistors (Q103) and (Q104). From the respective drain terminals of these two PMOS transistors (Q103) and (Q104), output currents I.sub.O1, I.sub.O2, are available, respectively. The differential output voltage V.sub.O1 -V.sub.O2 is produced in accordance with the impedance for each of the load circuit (3a) and (3b).
FIG. 16 shows a conventional CMFB circuit (2a). The circuit construction has been disclosed in a publication, IEEE Journal of Solid State Circuits, Vol.23, No.6, pp.1410-1414, December 1988 as in the tile of "Fully Differential Operational Amplifiers with Accurate Output balancing" by M. Banu, J. M. Khoury and Y. Tsividis.
In FIG. 16, the CMFB circuit (2a) is comprised of a buffer circuit (110), a voltage divider (111) and a sense amplifier (112). The buffer circuit (110) is comprised of two operational amplifier (OP1), (OP2). The voltage divider (111) is comprised of two resistors (R2), (R3) and two capacitors (C1), (C2). The sense amplifier (112) is constructed with two PMOS transistors (Q111), (Q112), two NMOS transistors (Q113), (Q114) and a constant-current source (113). The output voltages V.sub.O1, V.sub.O2 from the OTA (1) are applied to the buffer circuit (110). It is required, the input impedance of a buffer circuit to be as large as possible. Assuming a very high gain of OP1 and OP2, the gain of the buffer circuits become very closed to one.
When both of the two resistors (R2) and (R3) have the same resistance value and also both of the two capacitors (C1) and (C2) has the same capacitance value, a control voltage V.sub.Csens at the output of the voltage divider (111) is expressed by the following equation (1). EQU V.sub.Csens =(V.sub.O1 +V.sub.O2)/2=V.sub.cm (1a)
The voltage V.sub.cm is named as a common mode output voltage. The differential mode output voltage is defined as follows EQU V.sub.dm =(V.sub.O1 -V.sub.O2)/2 (1b)
According to (1a) and (1b) the output voltages V.sub.O1, and V.sub.O2 can be respectively expressed as follows. EQU V.sub.O1 =V.sub.dm +V.sub.cm, EQU V.sub.O2 =-V.sub.dm +V.sub.cm
The main function of a FB-OTA is suppression, or more precisely elimination in an ideal case, of a common mode component V.sub.cm at V.sub.o1 and V.sub.o2.
The sense amplifier (112) in the CMFB circuit (2a) compares the output voltage V.sub.C =V.sub.cm from the voltage divider (111) and a reference voltage V.sub.ref that is applied from the outside. The sense amplifier (112) provides a control voltage V.sub.B to OTA shown in FIG. 14 for which a common mode component at the OTA output voltages V.sub.o1, V.sub.o2 is strongly suppressing (eliminating in an ideal case). Practically, the common mode voltage V.sub.cm is eliminated with respect to the reference voltage V.sub.ref by using the feedback output from the CMFB circuit. However, as depicted in FIG. 16, the conventional CMFB circuit (2a) must be comprised of two operational amplifiers (OP1) and (OP2). Further the CMFB circuit (2a) must include the sense amplifier (112). This configuration arises many of serious problems for making the voltage/current converter in a small sized compact form and with limited amount of a power consumption.
Another type of the CMFB circuit (2a), which allows a power consumption to be limited, is shown in FIG. 17. This circuit configuration has been disclosed in a publication "CMOS Circuit Design, Layout and Simulation" by R. J. Baker, H. W. Li and D. E. Boyce.
The CMFB circuit (2a) construction shown in FIG. 17 includes a first sense differential pair (121) for comparing an input voltage V.sub.01 with a reference voltage V.sub.ref and a second sense differential pair (122) for comparing an input V.sub.O2 with the reference voltage V.sub.ref. A control voltage V.sub.B is produced by summing up the results of the first and second sense differential pairs (121) and (122),. This summing up is meant to compare the voltage (V.sub.O1 +V.sub.O2)/2 with the reference voltage V.sub.ref. Consequently, the CMFB circuit (2a) in FIG. 17 can achieve almost the same effect as using the circuit in FIG. 16. Consequently, the CMFB circuit in FIG. 17 can achieve similar effect without using the buffer circuit (110) and the voltage divider (111) such as shown in FIG. 16. However, a linearity of a CMFB circuit in FIG. 17 is very limited according to a low linearity of simple MOS differential pairs (121), (122).
Both of the CMFB circuits shown in FIGS. 16 and 17 are aimed to control the common mode output voltage V.sub.cm from the OTA.
The following equation expresses the relationship between the output common mode voltage V.sub.cm, the output common-mode current I.sub.cm and the load admittance Y of the voltage/current converter. EQU I.sub.cm =Y.multidot.V.sub.cm
According to the above equation, it can be pointed out that the output common-mode voltage from the voltage/current converter can also be controlled by the common-mode output current I.sub.cm.
A such construction of voltage/current converter circuit, based on employing of the output common-mode current I.sub.cm to control the OTA output currents, is shown in FIG. 18. This circuit has been disclosed in a publication of Japanese Institute of Electrical Engineers ECT-97-34, pp.13-16, May 1997 under a title of "A Single-Ended-Input Fully-Balanced-Output CMOS Circuit" by C. Wang, A. Hyogo and M. Ismail.
As similar to the converter shown in FIG. 14, the voltage/current converter in FIG. 18 includes an OTA(1) and a CMFB circuit(2a). The output terminals of the OTA(1) are coupled to load circuits (3a) and (3b), respectively. The OTA(1) comprises of an input section (11) for converting the input voltages V.sub.1, V.sub.2 to the output currents I.sub.O1, I.sub.O2. The output sections (12a) and (12b) are coupled to the input section (11). The output sections (12a) and (12b) are comprised of the same circuit construction. The CMFB circuit (2a) includes two current transfer sections (201a), (201b) and a control current generator (202). The current transfer sections (201a) and (201b) are constructed as the same circuit construction to the output sections (12a), (12b), respectively. The current transfer sections (201a), (201b) detect the output current I.sub.O1, I.sub.O2, respectively. The current outputs I.sub.O1 and I.sub.O2 are summed up and becomes a control current I.sub.C.
Similar as for output voltages V.sub.o1 and V.sub.o2 (see (1)), also for output currents I.sub.o1 and I.sub.o2, a differential mode current component I.sub.dm, and a common mode current component I.sub.cm can be defined. As a result the current outputs I.sub.O1, I.sub.O2 can be expressed as follows: EQU I.sub.O1 =I.sub.dm +I.sub.cm, (2a) EQU I.sub.O2 =-I.sub.dm +I.sub.cm (2b)
Consequently, the current I.sub.c becomes as the follow. EQU I.sub.c =I.sub.O1 +I.sub.O1 =2 I.sub.cm
Note the above control current I.sub.c includes a common mode current only.
In FIG. 18, the control current generating section (202) includes a pair of transistors Q121, Q122 for comprising a first current mirror circuit and a pair of transistors Q123, Q124 for comprising a second current mirror circuit, and a transistor Q125, an operational amplifier (OP3) and a resistor (R4). A current I.sub.ref passes through the transistor Q122 in the first current mirror circuit. Since a channel width of the transistor Q121 is provided so as to be a double channel width of the transistor Q122, a current passing through the transistor Q121 becomes 2I.sub.ref. Accordingly, the current 2 I.sub.ref passing through the transistor Q121 and the current I.sub.c passing through the current transfer section (201) are summed and becomes a current 2 I.sub.cm at a connecting node Nc of the transistor Q121 and the transistor Q124 in FIG. 18.
The connecting node Nc is coupled to a common gate terminal of the transistors Q126 and Q127 for constructing a bias circuit in the input section (11). Since the input impedance of the gates of the transistors Q126 and Q127 is almost infinite, the current I.sub.cm becomes equal to the reference current I.sub.ref.
However, the voltage/current converter shown in FIG. 18 needs a large chip area for installing the two current mirror circuits (Q121, Q122), (Q123, Q124), a resistor R4 and an operational amplifier OP3 in order to construct the CMFB circuit (2a). Further it needs a large amount of power consumption.
FIG. 19 shows a circuit construction of another example of a FB-OTA. The FB-OTA has been disclosed in a publication, IEEE Journal of Solid State Circuits, Vo.31, No.3, pp.321-330, March 1996 under a title "A Low-Distortion Bi-CMOS Seventh-Order Bessel Filter Operating at 2.5V Supply" by F. Yang, C. C. Enz. This FB-OTA also utilizes a common mode current output I.sub.cm from an OTA. The voltage/currents converter shown in FIG. 19 includes an OTA(1) and a CMFF circuit (2) for controlling a bias current in the OTA (1). The OTA (1) is comprised of a first circuit (211) for corresponding to an voltage input V.sub.1 and a second circuit (212) for corresponding to an voltage input V.sub.2. The first and second circuits are constructed in the same circuit construction.
The two MOS transistors (Q131) and (Q132) in the OTA (1) and a transistor (Q133) in the CMFF circuit (2) form a current mirror circuit. Accordingly, the transistors (Q131) and (Q132) in the OTA (1) have a current flow that is substantially equal to the current I.sub.c passing through the transistor (Q133) in the CMFF circuit (2). The two transistors (Q134) and (Q135) in the OTA(1) convert input voltages V.sub.1, V.sub.2 to output currents I.sub.1, I.sub.2. The CMFF circuit (2) has a substantially same circuit construction to the first and second circuits (211) and (212). However, in stead of using the transistors (Q134) and (Q135) in the first and second circuit, the CMFF circuit (2) has two transistors (Q136) and (Q137) connected in parallel, for the gate of which the input voltages V.sub.1, V.sub.2 are applied, respectively.
Even if each of the differential current outputs I.sub.1, I.sub.2 includes both of the differential mode current and a common mode current, the control current I.sub.C includes only a common mode current. Accordingly, by supplying the control current I.sub.C passing through the current mirror circuit to the OTA (1) as a bias current, the common mode included in the OTA input signals are eliminated.
The voltage/current converter shown in FIG. 19 has several benefits for making the apparatus in an easy design and making an operational speed of the apparatus faster due to supplying a control signal in a feedforward control. This can make faster than the apparatus of a feedback control. However, this voltage/current converter has another problem. That is, although this converter can eliminate the common mode signals included in the input signals V.sub.1, V.sub.2, it can not eliminate the common mode signals generated in the OTA (1).